1. The Field of the Invention
The present invention relates to signal processing. More specifically, the present invention relates to methods and systems for combining two or more channels of a received signal into one sub-channel so that certain signal processing may be performed on the sub-channel with fewer components than would be required to process the two or more channels separately.
2. Background and Related Art
Initially, satellite television systems included a single dish and a single receiver. With a single receiver, viewers had access to the large number of channels carried by a single satellite signal, but were able to view or record only one channel at any given time. Viewing different channels on separate televisions, recording one program while watching another, simultaneously recording two different programs, and using features like picture-in-picture were not possible. To complicate matters, the number of channels available to viewers and the average number of televisions served by a single satellite system have increased over time. Some satellite television systems are capable of simultaneously receiving signals from multiple satellites.
To solve these problems, satellite television service providers began offering multiple receivers to enhance the value of the service they provide. FIG. 1 illustrates one prior art system that includes multiple receivers. With multiple receivers, it is possible to view different channels on separate televisions, record one program while watching another, simultaneously record two different programs, use picture-in-picture, and the like. These options have been available for some time in the context of publicly broadcasted television programming because, as a general rule, separate tuners are implemented in each individual television and videocassette recorder (“VCR”). For picture-in-picture, a single television may include multiple tuners. As a result, consumers have grown to expect the foregoing features, without necessarily appreciating the need for or use of multiple tuners. Moreover, the market for televisions, VCRs, and the like, is such that broadcasters using public airwaves need not subsidize manufactures as a means of increasing market penetration.
In the prior art system of FIG. 1, multiple channels may be received over inputs 102. Input 102A and input 102B are used to indicate that channels may be provided by separate sources. Multiple receivers 112 tune channels for various devices 122. For example, receivers 112A and 112B tune different channels for display devices 122A and 122B. Note that receiver 112B is connected to both input 102A and input 102B, and therefore, is capable of tuning channels from separate sources. Receivers 112C and 112D tune different channels for VCRs 122C and 122D. As described above, with multiple tuners it is possible to view and/or record different channels simultaneously. Both receiver 112E and receiver 112F are connected to display 122E to provide picture-in-picture capability.
However, satellite service providers face some challenges that are relatively specific to the industry. Market considerations may make it difficult to charge more than a nominal fee for each additional receiver. Furthermore, fierce competition has lead satellite service providers to subsidize the expense of receivers to consumers, on the theory that the subsidy can be recouped over time through programming charges. As a result, providing additional receivers at a nominal price significantly prolongs the time required for satellite service providers to recover the costs associated with supplying receivers. Therefore, methods and systems, such as the system illustrated in FIG. 2 and discussed in more detail below, capable of simultaneously processing multiple channels at a relatively low cost are desired.
Turning next to FIGS. 3A-3D, the block diagrams illustrating certain portions of a system that uses direct down conversion rather than the present invention will be described. FIGS. 3A-3D and the corresponding discussion are included here to provide context for the present invention and are not an admission of prior art in any degree. The system is capable of simultaneously tuning up to eight channels. Components that are part of the processing for a particular channel are labeled with a numeric suffix, “1” for the first channel, “2” for the second channel, and so on. Those of skill in the art will recognize that the components shown in FIGS. 3A-3D do not necessarily represent individual physical components, but rather may represent collections of physical components to accomplish a particular task or goal.
Beginning with the analog processing shown in FIG. 3A, RF switch 312 receives an L-band radio frequency input signal that is approximately 1 GHz wide (from about 900 MHz to about 2200 MHz). The input signal contains multiple transponder channels that may be referred to as simply transponders or channels. Wide-band low noise amplifier (“LNA WB”) 316 ensures that the received signal power level is sufficient for the processing that follows. Signals outside of the bandwidth of interest are rejected by wide-band band pass filter (“BPF WB”) 322. Eight frequency synthesizers 328 use crystal oscillator 326 to generate appropriate frequencies for directly converting one or more channels to baseband.
Mixers 332 mix the frequencies supplied by frequency synthesizers 328 with the received input signal to directly convert each of the eight channels to baseband. 90-degree phase splitters 334 provide two versions of each frequency generated by frequency synthesizers 328, 90-degrees out of phase with each other, to separate the in-phase (I) and quadrature (Q) components of each channel. Frequency synthesizers 328 are tuned by synthesizer control module 306. (Of the sixteen mixers 332 and the eight phase splitters 334, only mixers 332-1A and 332-1B, and phase splitters 334-1 are shown.) Note that at this point, each of the eight channels has been divided into an I and Q component channel, for a total of sixteen component channels that undergo a significant amount of separate processing.
Each of the sixteen component channels (I and Q components for each of eight channels) is amplified by one of the amplifiers (“AMP”) 336, then passes through one of the variable low pass filters (“LPF”) 338, and is converted from analog to digital by one of the analog to digital converters (“A/D”) 342 at a sampling frequency of Fs. The cut-off frequency for each LPF 338 is controlled through filter control module 302 to account for diverse symbol rates. (Again, of the sixteen amplifiers 336, sixteen low pass filters 338, and sixteen analog to digital converters 342, only AMPs 336-1A and 336-1B, and LPFs 338-1A and 338-1B, and A/Ds 342-1A and 342-1B are shown.) The gain for each of the amplifiers 336 is controlled by an automatic gain control signal (e.g., AGC 1,1) that establishes an appropriate signal level for the operation of analog to digital converters 342.
Analog to digital converters 342 are shown in dashed lines to indicate that the analog processing for direct down conversion may be part of the analog processing shown in FIG. 3A or part of the digital processing that is discussed with reference to FIGS. 3B-3-D. This also explains the presence of analog signals, such as AS1_I and AS1_Q, and digital signals, such as DS1_I and DS1_Q, for each channel. Typically, only one or the other is available. Those of skill in the art will recognize that significant costs and problems may occur in attempting to place sixteen amplifiers and sixteen analog to digital converters (with eight bits each for 128 lines total) in relatively close proximity, such as within a single integrated circuit. Among other things, such a large number of analog components requires substantial space to ensure proper heat dissipation and to avoid unacceptable levels of crosstalk between the individual component signals.
As described above, the analog to digital converters 342 shown in FIG. 3B may be included within the analog processing of FIG. 3A or the digital processing of FIGS. 3B-3D. Note that only the processing of the first channel is shown to simplify the drawings. Although not shown, the other seven channels are processed in a similar fashion. If signals are present for the first channel (i.e., the first channel is being tuned), switch 346 passes the I and Q signal components on for further processing. Note that automatic gain control 348 monitors the signal levels produced by analog to digital converters 342 so that the gain of amplifiers 336 may be adjusted accordingly. DC offset filter 352, with components 352-1A and 352-1B, removes DC bias from the digital representations of the I and Q components of the first channel.
FIG. 3B also shows a clock tree and several interfaces. In clock network 362, all independent clocks are synchronized. External microprocessor interface 364 provides for communication with an external microprocessor. Analog filter control interface 366 is used to control the variable analog filters through filter control module 302 (FIG. 3A), such as by altering the cut-off frequency based on symbol rate. Frequency synthesizer control interface 368 tunes the frequency synthesizers through frequency synthesizer control module 306 (FIG. 3A) to produce the signals used in directly down converting to baseband.
Because the processing 370-1 of FIG. 3C is similar to the processing of FIG. 4C, it will be described here from a relatively high-level perspective. During processing 370-1, amplitude and phase imbalance between the I and Q components of a tuned channel are removed. Because the sampling frequency accounts for a range of symbol rates, low symbol rate signals are likely to be oversampled and undergo decimation and filtering. Additional filtering accounts for power spectral shaping that may be performed by the signal transmitter. Finally, frequency and/or phase offsets that may result in constellation shifts are removed.
The processing 390-1 shown in FIG. 3D likewise will be described in somewhat greater detail with respect to FIG. 4D, below. At this stage of the processing, the channel as transmitted has been essentially recovered and what remains is to arrange and organize the channel content so that the content is in a format that can be displayed. Processing 390-1 includes a Viterbi decoder/synchronizer, a Reed-Solomon synchronizer, a convolution deinterleaver, a Reed-Solomon decoder, and a descrambler.
Note that in the tuner implementation of FIGS. 3A-3D, each tuned channel of the input signal was immediately converted to baseband and separated into its I and Q components, resulting in sixteen separate signal paths when simultaneously tuning eight separate channels. As a result, it may be difficult or impossible to implement the needed analog processing (e.g., sixteen control amplifiers and sixteen separate analog to digital converters) within a single integrated circuit due to interference between channels, heat dissipation problems, power consumption, and the like. Therefore, a receiver capable of simultaneously tuning eight channels and implemented using direct down conversion as shown in FIGS. 3A-3D, generally will be more expensive and less reliable than one implementing the present invention as described with respect to FIGS. 4A-4D.